| 18 September |
Welcome
Mr. David Martinez / MIT Lincoln Laboratory |
Mission Keynote Speaker
Dr. Michael McGrath / Department of the Navy, Research, Development & Acquisition
Electronic files not available |
Technology Keynote Speaker: The Impact of Multicore on Math Software
Prof. Jack Dongarra / University of Tennessee, ICL
Abstract | Presentation - PDF |
Opening Remarks
Mr. Robert Bond / MIT Lincoln Laboratory
Presentation - PDF || Presentation - PPT
|
Session 1: Multicore Technologies
Chair: Michael Vai / MIT Lincoln Laboratory
Introduction - PDF || Introduction - PPT |
StreamIt—A Programming Language for the Era of Multicores
Saman Amarasinghe / Massachusetts Institute of Technology CSAIL
Presentation - PDF || Presentation - PPT |
World’s First Polymorphic Computer—MONARCH
Lloyd Lewins / Raytheon Company
*Kenneth Prager / Raytheon Company
Gillian Groves / Raytheon Company
Michael Vahey / Raytheon Company
Abstract | Presentation - PDF || Presentation - PPT |
Advanced Programming and Execution Models for Future Multi-Core Systems
Hans Zima / Jet Propulsion Laboratory, California Institute of Technology; Institute of Scientific Computing, University of Vienna, Austria
Abstract | Presentation - PDF || Presentation - PPT
|
Poster / Demo A: Advanced Algorithms and Hardware
Chair: Michael Vai / MIT Lincoln Laboratory |
| Poster / Demo A Précis |
| Poster A.1 |
ALPS: Software Framework for Scheduling Parallel Computations with Application to Parallel Space-Time Adaptive Processing
Kyusoon Lee / Cornell University
Adam Bojanczyk / Cornell University
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster A.2 |
A Clustered Multiprocessor and Its Multicore Building Block
Matthew Reilly / SiCortex, Inc.
Abstract | Précis - PDF || Précis - PPT |
| Poster A.3 |
NMP ST8 Dependable Multiprocessor
John Samson / Honeywell International
Alan George / University of Florida
Rafi Some / Jet Propulsion Laboratory, California Institute of Technology
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster A.4 |
DMAGIC: A High-level Partitioning Methodology for Discrete Signal Transforms onto Distributed Hardware Architectures
Rafael Arce-Nazario / University of Puerto Rico, Mayagüez
Manuel Jiménez / University of Puerto Rico, Mayagüez
Domingo Rodríguez / University of Puerto Rico, Mayagüez
Abstract | Précis - PDF || Précis - PPT |
| Poster A.5 |
Terabyte ToKuSampleSort
Bradley Kuszmaul / Massachusetts Institute of Technology CSAIL, Tokutek, Inc., Clik Arts Inc., and MIT Lincoln Laboratory
Abstract | Précis - PDF |
| Poster A.6 |
Use of Dense Wavelength Division Multiplexing (DWDM) Optical Interconnects to Improve Parallel and Distributed Processing Architecture Connectivity
Rick Stevens / Lockheed Martin Corporation
Greg Whaley / Lockheed Martin Corporation
Roger Karnopp / Lockheed Martin Corporation
Howard Schantz / Lockheed Martin Corporation
Mert Horne / Lockheed Martin Corporation
Abstract | Précis - PDF || Précis - PPT |
| Poster A.7 |
Performance of Direct Attached Disk Subsystems
Roger Chamberlain / Washington University in St. Louis and Exegy, Inc.
Berkley Shands / Washington University in St. Louis
Abstract | Précis - PDF || Précis - PPT |
| Poster A.8 |
When Storage Devices Become Computers
Robert Thibadeau / Seagate Research
*Kevin Gomez / Seagate Research
Tom Mitchell / Carnegie Mellon University
David Touretzky / Carnegie Mellon University
Terrence Sejnowski / Salk Institute
Electronic files not available |
| Poster A.9 |
Low Latency Real-Time Computing on Multiprocessor Systems Running Standard Linux
Dimitri Sivanich / SGI
Abstract | Précis | Poster - PDF || Précis - PPT |
| Poster A.10 |
Optimization of Memory Allocation in VSIPL
Jinwoo Suh / University of Southern California, ISI
Janice McMahon / University of Southern California, ISI
Stephen Crago / University of Southern California, ISI
Dong-In Kang / University of Southern California, ISI
Abstract | Précis - PDF || Précis - PPT |
| Poster A.11 |
Use of Python as a Matlab Replacement for Algorithm Development and Execution in a Multi-Core Environment
Glen Mabey / Southwest Research Institute
Brian Granger / Tech-X Corporation
Abstract | Précis - PDF || Précis - PPT |
| Poster A.12 |
Automatic Deployment of Streaming Applications on Hybrid Architectures
Roger Chamberlain / Washington University in St. Louis
Mark Franklin / Washington University in St. Louis
Abstract | Précis - PDF || Précis - PPT |
| Poster A.13 |
Multiprocessor Implementation of a Face Detection System
Sankalita Saha / University of Maryland, College Park
Neal Bambha / US Army Research Laboratory
*Shuvra Bhattacharyya / University of Maryland, College Park
Abstract | Précis - PDF || Précis - PPT |
| Poster A.14 |
Synthesizing Parallel Programming Models for Asymmetric Multi-core Systems
Dimitris Nikolopoulos / Virginia Tech
Kirk Cameron / Virginia Tech
Abstract | Précis - PDF || Précis - PPT |
| Poster A.15 |
Benchmarking Publish/Subscribe Middleware for Radar Applications
Andrew Rhoades / MIT Lincoln Laboratory
Glenn Schrader / MIT Lincoln Laboratory
Paul Poulin / MIT Lincoln Laboratory
Abstract | Précis - PDF |
|
Session 2: Runtime Optimization
Chair: Joel Goodman / MIT Lincoln Laboratory
Introduction – PDF || Introduction - PPT |
TX-2500—An Interactive, On-Demand Rapid-Prototyping HPC System
Albert Reuther / MIT Lincoln Laboratory
Bill Arcand / MIT Lincoln Laboratory
Tim Currie / MIT Lincoln Laboratory
Andy Funk / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln
Laboratory
Matthew Hubbell / MIT Lincoln Laboratory
Andrew McCabe / MIT Lincoln Laboratory
Peter Michaleas / MIT Lincoln Laboratory
Abstract | Presentation – PDF || Presentation – PPT |
Thimble: Design-time Analysis of Multi-threaded System Behavior
Daniel Waddington / Lockheed Martin Corporation
Abstract | Presentation – PDF || Presentation – PPT |
Preliminary Study toward Intelligent Run-time Resource Management Techniques for Large Tiled Multi-Core Architectures
Dong-In Kang / University of Southern California, ISI
Jinwoo Suh / University of Southern California, ISI
Janice McMahon / University of Southern California, ISI
Stephen Crago / University of Southern California, ISI
Abstract | Presentation – PDF || Presentation – PPT |
HPC Processor Trends from High-end to Volume, Small, Large, Open, or Embedded
David Scott / Intel Corporation
Abstract | Presentation - PDF |
Research Challenges for the Next Decade
Zachary Lemnios / MIT Lincoln Laboratory
Presentation - PDF || Presentation - PPT |
Closing Remarks
Jeremy Kepner / MIT Lincoln Laboratory |
Banquet Speaker: American Innovator
Mr. Doug Malewicki / AeroVisions, Inc.
|
19 September
|
Session 3: Multicore Hardware Challenges
Chair: Robert Bond / MIT Lincoln Laboratory
Introduction – PDF || Introduction - PPT |
The Tile Processor: A 64-Core Multicore for Embedded Processing
Anant Agarwal / Massachusetts Institute of Technology CSAIL
Presentation - PDF || Presentation - PPT |
Beyond Multi-core: The Dawning of the Era of Tera, Intel™ 80-core Tera-scale Research Processor
James Held / Intel Corporation
Abstract | Presentation – PDF || Presentation - PPT |
Using Industry Standards to Exploit the Advantages and Resolve the Challenges of Multicore Technology
Markus Levy / The Multicore Association and The Embedded Microprocessor Benchmark Consortium
Abstract | Presentation – PDF || Presentation - PPT |
Amenability of Multigrid Computations to FPGA-Based Acceleration
Yongfeng Gu / Boston University
*Martin Herbordt / Boston University
Abstract | Presentation - PDF
Presentation - PPT
High Performance Parallel Implementation of Adaptive Beamforming Using Sinusoidal Dithers
Peter Vouras / The Johns Hopkins University
Trac Tran / The Johns Hopkins University
Abstract | Presentation - PDF
Presentation - PPT |
Focus 3: Cell
Chair: Sharon Sacco / MIT Lincoln Laboratory
Introduction - PDF | Introduction - PPT |
FFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine
David Bader / Georgia Institute of Technology
*Virat Agarwal / Georgia Institute of Technology
Abstract | Presentation - PDF || Presentation - PPT
Implementation of SIGINT Application on CELL-BE
Richard Besler / Black River Systems Company
Emily Krzysiak / Air Force Research Laboratory
Electronic files not available
Performance of a Multicore Matrix Multiplication Library
Frank Lauginiger / Mercury Computer Systems, Inc.
*Robert Cooper / Mercury Computer Systems, Inc.
Jonathan Greene / Mercury Computer Systems, Inc.
Michael Pepe / Mercury Computer Systems, Inc.
Myra Jean Prelle / Mercury Computer Systems, Inc.
Abstract | Presentation - PDF || Presentation - PPT |
|
Poster / Demo B: FPGA Technologies and Applications
Chair: Robert Bond / MIT Lincoln Laboratory |
| Poster / Demo B Précis |
| Poster B.1 |
Evaluating Partial Reconfiguration for Embedded FPGA Applications
Ross Hymel / University of Florida
Alan George / University of Florida
*Chris Conger / University of Florida
Herman Lam / University of Florida
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster B.2 |
A Streaming FFT on 3GSPS ADC Data using Core Libraries and DIME-C
Robin Bruce / Institute of System Level Integration, Alba Centre
*Malachy
Devlin / Nallatech
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster B.3 |
Accelerating Algorithm Implementation in FPGA/ASIC Using Python
Tom Dillon / Dillon Engineering, Inc.
Jeremy Paatela / Dillon Engineering, Inc.
Guenter Dannoritzer / Dillon Engineering, Inc.
Scott Hussong / Dillon Engineering, Inc.
Abstract | Précis || Poster - PDF |
| Poster B.4 |
Phase Unwrapping on Reconfigurable Hardware
Sherman Braganza / Northeastern University
Miriam Leeser / Northeastern University
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster B.5 |
SmartCell: A Coarse-Grained Reconfigurable Architecture for High Performance and Low Power Embedded Computing
Xinming Huang / Worcester Polytechnic Institute
Abstract | Précis - PDF || Précis - PPT |
| Poster B.6 |
Accelerating Genome Sequencing 100X with FPGAs
Olaf Storaasli / Oak Ridge National Laboratory
Abstract | Précis - PDF || Précis - PPT |
| Poster B.7 |
Prototyping Advanced Military Sensor Systems Using FPGA-to-ASIC Design Flow
J. Ryan Kenny / Altera Corporation
Jeff Wills / Altera Corporation
Rick Pancoast / Lockheed Martin Corporation
Ellis Taliaferro / Lockheed Martin Corporation
Abstract | Précis - PDF || Précis - PPT |
| Poster B.8 |
Digital Beam Former Coefficient Management Using Advanced Embedded Processor Technology
J. Ryan Kenny / Altera Corporation
Argy Krikelis / Altera Corporation
Abstract | Précis - PDF || Précis - PPT |
| Poster B.9 |
FPGA Coprocessing in Multi-Core Architectures for DSP
J. Ryan Kenny / Altera Corporation
Bryce Mackin / Altera Corporation
Abstract | Précis - PDF || Précis - PPT |
| Poster B.10 |
Transformation of Sequential Software into Parallel FPGA Hardware: A Case Study Using the SPEC CPU 2006 Benchmark
Raymond Hoare / Concurrent EDA, LLC
Abstract | Précis - PDF || Précis - PPT |
| Poster B.11 |
FPGA-Based Acceleration of an Image Registration Algorithm
Jay Brockman / University of Notre Dame
Daniel Rinzler / University of Notre Dame
Peter Bui / University of Notre Dame
Frank Iannarilli / Aerodyne Research, Inc.
Abstract | Précis - PDF || Précis - PPT |
| Poster B.12 |
Applying Open Standards to FPGA IP Interfaces
Shepard Siegel / Mercury Computer Systems, Inc.
Abstract | Précis - PDF || Précis - PPT |
| Poster B.13 |
FPGA Based Systolic Array Implementation of QR Transformation Using Givens Rotations
Xiaojun Wang / Northeastern University
Miriam Leeser / Northeastern University
Abstract | Précis - PDF || Précis - PPT |
|
Session 4: Novel Applications
Chair: David Cousins / BBN Technologies |
Focus 4: GPUs
Chair: Craig Lund / Mercury Computer Systems
Introduction - PDF ||
Introduction - PPT |
Projective Transform on Cell: A Case Study
Sharon Sacco / MIT Lincoln Laboratory
Hahn Kim / MIT Lincoln Laboratory
Sanjeev Mohindra / MIT Lincoln Laboratory
Peter Boettcher / MIT Lincoln Laboratory
Chris Bowen / MIT Lincoln Laboratory
Nadya Bliss / MIT Lincoln Laboratory
Glenn Schrader / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Abstract | Presentation - PDF ||
Presentation - PPT
Toward Fast Computation of Dense Image Correspondence on the GPU
Mark Duchaineau / Lawrence Livermore National Laboratory
Jonathan Cohen / Lawrence Livermore National Laboratory
Sheila Vaidya / Lawrence Livermore National Laboratory
Abstract | Presentation - PDF ||
Presentation - PPT
Analysis and Mapping of Sparse Matrix Computations
Nadya Bliss / MIT Lincoln Laboratory
Sanjeev Mohindra / MIT Lincoln Laboratory
Varun Aggarwal / Massachusetts Institute of Technology
Una-May O’Reilly / Massachusetts Institute of Technology
CSAIL
Abstract | Presentation - PDF || Presentation – PPT
Panel: Multicore Meltdown? Moderator: Dr. James C. Anderson / MIT Lincoln Laboratory
Presentation - PDF || Presentation - PPT
Distinguished Panelists:
Dr. James Held / Intel Corporation
Dr. Jeremy Kepner / MIT Lincoln Laboratory
Mr. Greg Rocco / Mercury Computer Systems, Inc.
Mr. Kalpesh Sheth / Advanced Processing Group, DRS Technologies
Presentation - PDF || Presentation - PPT
Dr. Thomas VanCourt / Altera Corporation |
Are Graphics Processors the New Supercomputers?
Norman Rubin / ATI Research
Abstract | Presentation - PDF || Presentation - PPT
Benchmarking the NVIDIA 8800GTX with CUDA Development Platform
Michael McGraw-Herdeg / Massachusetts Institute of Technology
*Douglas Enright / The Aerospace Corporation
B. Scott Michel / The Aerospace Corporation
Abstract | Presentation - PDF || Presentation - PPT
FFTs of Arbitrary Dimensions on GPUs
Xiaobai Sun / Duke University
Nikos Pitsianis / Duke University
Abstract | Presentation – PDF ||
Presentation – PPT
DARPA STAT BOY: Fast Hybrid QR-Cholesky Factorization and Tuning Techniques for STAP Algorithm Implementation on GPU Architectures
Dennis Healy / DARPA
*Dennis Braunreiter / SAIC
Jackie Sillaci / SAIC
David Boe / SAIC
Jeremy Furtek / SAIC
Xaiobai Sun / Duke University
Abstract | Presentation - PDF ||
Presentation - PPT |
20 September
|
Session 5: Multicore Environments
Chair: Robert Bond / MIT Lincoln Laboratory
Introduction - PDF || Introduction - PPT |
High Performance Simulations of Electrochemical Models on the Cell Broadband Engine
James Geraci / Massachusetts Institute of Technology
Sudarshan Raghunathan / Massachusetts Institute of Technology
Abstract | Presentation - PDF || Presentation - PPT |
Sourcery VSIPL++ for the Cell/B.E.
Jules Bergmann / CodeSourcery, Inc.
Mark Mitchell / CodeSourcery, Inc.
Don McCoy / CodeSourcery, Inc.
Stefan Seefeld / CodeSourcery, Inc.
Assem Salama / CodeSourcery, Inc.
Fred Christensen / IBM
Thomas Steck / Lockheed Martin Corporation
Abstract | Presentation - PDF || Presentation - PPT |
Programming Examples that Expose Efficiency Issues for the Cell Broadband Engine Architecture
William Lundgren / Gedae, Inc.
Rick Pancoast / Lockheed Martin Corporation
David Erb / IBM
Kerry Barnes / Gedae, Inc.
James Steed / Gedae, Inc.
Abstract | Presentation - PDF || Presentation - PPT |
PVTOL: A High-Level Signal Processing Library for Multicore Processors
Hahn Kim / MIT Lincoln Laboratory
Nadya Travinin Bliss / MIT Lincoln Laboratory
Ryan Haney / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Sanjeev Mohindra / MIT Lincoln Laboratory
Sharon Sacco / MIT Lincoln Laboratory
Glenn Schrader / MIT Lincoln Laboratory
Edward Rutledge / MIT Lincoln Laboratory
Abstract | Presentation - PDF || Presentation - PPT
Defense Applications Implemented Utilizing the Parallel Processing Features of Sourcery VSIPL++
Thomas Steck / Lockheed Martin Corporation
Rick Pancoast / Lockheed Martin Corporation
Ellis Taliaferro / Lockheed Martin Corporation
Jules Bergmann / CodeSourcery, Inc.
Electronic files not available |
Application-Level Benchmarking with Synthetic Aperture Radar
Chris Conger / University of Florida
Adam Jacobs / University of Florida
Alan George / University of Florida
Abstract | Presentation - PDF ||
Presentation - PPT
A Survey of Multi-Core Coarse-Grained Reconfigurable Arrays for Embedded Applications
Justin Tripp / Los Alamos National Laboratory
Jan Frigo / Los Alamos National Laboratory
Paul Graham / Los Alamos National Laboratory
Abstract | Presentation - PDF
Exploring Multi-core Processors Using Realistic Signal- and Image-processing Application Benchmarks
Ray Artz / Lockheed Martin Corporation
Brian Loe / Lockheed Martin Corporation
Janet Pavelich / Lockheed Martin Corporation
Jules Bergmann / CodeSourcery, Inc.
Abstract | Presentation - PDF ||
Presentation - PPT |
Poster / Demo C: Cell / GPU Technologies
Chair: Robert Bond / MIT Lincoln Laboratory |
| Poster / Demo C Précis |
| Poster C.1 |
Hardware and Compute Abstraction Layers for Accelerated Computing Using Graphics Hardware and Conventional CPUs
Justin Hensley / Advanced Micro Devices, Inc.
Abstract | Précis - PDF || Précis - PPT |
| Poster C.2 |
Gedae Portability: From Simulation to DSPs to the Cell Broadband Engine
James Steed / Gedae, Inc.
William Lundgren / Gedae, Inc.
Kerry Barnes / Gedae, Inc.
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster C.3 |
Accelerating MATLAB with CUDA
Massimiliano Fatica / NVIDIA Corporation
Won-Ki Jeong / University of Utah
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster C.4 |
Implementation of Parallel Processing Techniques on Graphical Processing Units
Brad Baker / General Dynamics
Wayne Haney / General Dynamics
Charles Choi / General Dynamics
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster C.5 |
R-Verify™: Deep Checking of Embedded Code
James Ezick / Reservoir Labs, Inc.
Donald Nguyen / Reservoir Labs, Inc.
Richard Lethin / Reservoir Labs, Inc.
Rick Pancoast / Lockheed Martin Corporation
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster C.6 |
Dependable Multiprocessing with the Cell Broadband Engine
David Bueno / Honeywell, Inc.
Matt Clark / Honeywell, Inc.
John Samson, Jr. / Honeywell, Inc.
Adam Jacobs / University of Florida
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster C.7 |
Chirp Radar Parameter Estimators over Distributed Hardware Structures
Cesar Aceros-Moreno / University of Puerto Rico, Mayagüez
Ana Ramirez / University of Puerto Rico, Mayagüez
Domingo Rodriguez / University of Puerto Rico, Mayagüez
Electronic files not available |
| Poster C.8 |
Introduction of Error Correcting Schemes in the Design Process of Self-Healing Circuits for Nanoscale Fabrics
Catherine Dezan / Université de Bretagne Occidentale
*Teng Wang / University of Massachusetts
Abstract | Précis - PDF || Précis - PPT |
| Poster C.9 |
Development and Performance Analysis of a Distributed Corner Turn using the AXIS Graphical Software System
Thomas Litrenta / Radstone Embedded Systems
Abstract | Précis - PDF || Précis - PPT |
| Poster C.10 |
Multi-core Programming Frameworks for Embedded Systems
Kaushal Sanghai / Analog Devices, Inc.
Rick Gentile / Analog Devices, Inc.
Abstract | Précis | Poster - PDF || Précis | Poster - PPT |
| Poster C.11 |
Real-time Multi-core PDE-Solvers in LabVIEW
Shawn McCaslin / National Instruments
Michael Cerna / National Instruments
Michael Chen / National Instruments
Nanxiong Zhang / National Instruments
Bin Wang / National Instruments
Lothar Wenzel / National Instruments
Abstract | Précis - PDF || Précis - PPT |
| Poster C.12 |
Announcing PWRficient Processors from PA Semi, the Most Power-Efficient, High-Performance Processors Available
Pete Bannon / P.A. Semi
Abstract | Précis - PDF |
| Poster C.13 |
Efficient Memorization Strategies for Object Recognition with a Multi-Core Architecture
George Viamontes / Lockheed Martin Corporation
Mohammed Amduka / Lockheed Martin Corporation
Jon Russo / Lockheed Martin Corporation
Matthew Craven / Lockheed Martin Corporation
Thanh Vu Nguyen / Lockheed Martin Corporation
Précis - PDF || Précis – PPT |
|
Session 6: Awards Session
Jeremy Kepner / MIT Lincoln Laboratory |
Vforce: Aiding the Productivity and Portability in Reconfigurable Supercomputer Applications via Runtime Hardware Binding
Nicholas Moore / Northeastern University
Miriam Leeser / Northeastern University
Laurie Smith King / College of the Holy Cross
Abstract | Presentation - PDF || Presentation - PPT |
On-Chip Photonic Communications for High-Performance Multi-Core Processors
Keren Bergman / Columbia University
Luca Carloni / Columbia University
Abstract | Presentation - PDF || Presentation - PPT |
Implementation of Polar Format SAR Image Formation on the IBM Cell Broadband Engine
Jeffrey Rudin / Mercury Computer Systems, Inc.
Abstract | Presentation - PDF |
POD: A Parallel-On-Die Architecture
Dong Hyuk Woo / Georgia Institute of Technology
Joshua Fryman / Intel Research Berkeley
Allan Knies / Georgia Institute of Technology
Marsha Eng / Intel Corporation
Hsien-Hsin Lee / Georgia Institute of Technology
Abstract | Presentation - PDF || Presentation - PPT |
Multithreaded Programming in Cilk
Matteo Frigo / Cilk Arts
Abstract | Presentation - PDF |