HPEC 2004 Proceedings *Denotes outstanding submission |
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| 28 September |
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| AUDITORIUM |
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Welcome David Martinez / MIT Lincoln Laboratory |
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Opening
Remarks Robert Bond / MIT Lincoln Laboratory |
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| Supercomputing:
Trends, Performance Measurement, and Opportunities (Invited) |
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Session
1: Emerging Technologies Kenneth Teitelbaum / MIT Lincoln Laboratories |
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Future
Prospects for Moore's Law (Invited) Dr. Robert Doering / Texas Instruments Abstract || Presentation - PDF | Presentation - PPT |
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| Break |
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The
Evaluation of GPU-Based Programming Environments for Knowledge Discovery John Johnson / Lawrence Livermore National Library Randall Frank / Lawrence Livermore National Library Sheila Vaidya / Lawrence Livermore National Library Abstract || Presentation -PDF | Presentation - PPT |
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Sustaining
the Exponential Growth of Embedded Digital Signal Processing Capability Gary Shaw / MIT Lincoln Laboratory Mark Richards / Georgia Institute of Technology Abstract || Presentation PDF | Presentation - PPT |
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Poster
/ Demo A: High Level Environments and Interconnects Albert Reuther / Lincoln Laboratory |
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| Poster
Session A Précis |
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| Poster
A.1 |
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| Poster
A.2 |
Software
Architecture for Morphing in Polymorphous Computing Architectures Dan Campbell / Georgia Institute of Technology Dennis Cottel / SPAWAR Systems Center Randall Judd / SPAWAR Systems Center Mark Richards / Georgia Institute of Technology Abstract || Précis || Poster - PDF | Précis || Poster - PPT |
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| Poster
A.3 |
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| Poster
A.4 |
pMatlab
Takes the HPCchallenge Ryan Haney / MIT Lincoln Laboratory Andrew Funk / MIT Lincoln Laboratory Jeremy Kepner / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Charles Rader / MIT Lincoln Laboratory Albert Reuther / MIT Lincoln Laboratory Nadya Travinin / MIT Lincoln Laboratory Abstract || Précis || Poster - PDF | Précis - PPT |
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| Poster
A.5 |
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| Poster
A.6 |
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| Poster
A.7 |
Benchmarking
Microprocessors for High-End Signal Processing |
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| Poster A.8
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Processing
Challenges in Shrinking HPEC Systems into Small UAVs |
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| Poster
A.9 |
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| Poster
A.10 |
The
Devlopment of a Tactical Environmental Processor (TEP) Open Architecture
(OA) Application Using Middleware Standard APIs Bonnie Vena / Lockheed Martin MS&S Carl Barberi / Lockheed Martin MS&S Steve Paavola / SKY Computers, Inc. |
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Session
2: Novel Systems Michael Harris / BAE Space Systems IEWS |
Focus
1: Advanced Software Optimization |
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Deployment
of SAR and GMTI Signal Processing on a Boeing 707 Aircraft using pMatlab
and a Bladed Linux Cluster Jeremy Kepner / MIT Lincoln Laboratory Tim Currie / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Bipin Mathew / MIT Lincoln Laboratory Andrew McCabe / MIT Lincoln Laboratory Michael Moore / MIT Lincoln Laboratory Daniel Rabinkin / MIT Lincoln Laboratory Albert Reuther / MIT Lincoln Laboratory Andrew Rhoades / MIT Lincoln Laboratory Louis Tella / MIT Lincoln Laboratory Nadya Travinn / / MIT Lincoln Laboratory Abstract || Presentation - PDF | Presentation - PPT |
Discrete
Fourier Transform IP Generator |
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Virtual
Prototyping and Performance Analysis of RapdIO-Based System Architectures
for Space-Based Radar David Bueno / University of Florida Chris Conger / University of Florida Alan George / University of Florida Adam Leko / University of Florida Ian Troxel / University of Florida Abstract || Presentation - PDF | Presentation - PPT |
Mapping
Signal Processing Kernels to Tiled Architectures |
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| Kronecker-FFT
Algorithms for Multidimensional SAR PSF Processing Domingo Rodriquez / University of Puerto Rico Abstract |
A
Transformational Approach to High Performance Embedded Computing |
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| A
KASSPER Real-Time Signal Processor Testbed Glen Schrader / MIT Lincoln Laboratory Abstract || Presentation - PDF | Presentation - PPT |
Adaptive
Mapping of Linear DSP Algorithms to Fixed-Point Arithmetic |
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HPCS
HPCchallenge Benchmark Suite David Koester / The MITRE Corporation Jack Dongarra / University of Tennessee Piotr Luszczek / Innovative Computing Laboratory Abstract || Presentation - PDF | Presentation - PPT |
Language-level
Transactions for Modular Reliable Systems |
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| SAE
AADL: An Industry Standard for Predictable Embedded Real-Time
Systems Engineering (Invited) |
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| Banquet
Presentation Area-Time-Power Tradeoffs in Computer Design: The Road Ahead Dr. Michael Flynn / Stanford University Presentation - PDF | Presentation - PPT |
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| 29 September |
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| Announcements Robert Bond / MIT Lincoln Laboratory |
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| Keynote
Address |
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| Session
3: FPGAs John Grosh / OSD |
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| Industry
Chip Hardware Technology (Invited) H. Peter Hofstee / IBM |
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| FPGA
Acceleration of Information Management Services Richard Linderman / AFRL Chun-Shin Lin / University of Missouri, Columbia Mark Linderman / AFRL Abstract || Presentation - PDF | Presentation - PPT |
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| A
Systolic FFT Architecture for Real Time FPGA Systems Preston Jackson / MIT Lincoln Laboratory Cy Chan / MIT Lincoln Laboratory Charles Rader / MIT Lincoln Laboratory Jonathan Scalera / MIT Lincoln Laboratory Michael Vai / MIT Lincoln Laboratory Abstract || Presentation - PDF | Presentation - PPT |
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| Variable
Precision Floating Point Division and Square Root Miriam Leeser / Northeastern University Albert Conti / Northeastern University Xiaojun Wang / Northeastern University Abstract || Presentation - PDF | Presentation - PPT |
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| Poster
/ Demo B: Dynamic Hardware Michael Vai / MIT Lincoln Laboratory |
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| Poster
Session B Précis |
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| Poster
B.1 |
Automated
Incremental Design of Flexible Instrusion Detection Systems on FPGAs Zachary Baker / University of Southern California Viktor Prasanna / University of Southern California Ronald Scrofano / University of Southern California Abstract || Précis || Presentation - PDF | Précis || Poster - PPT |
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| Poster
B.2 |
Reconfigurable
Computing for Embedded Systems, FPGA Devices and Software Components Graham Bardouleau / Mercury Computer Systems, Inc. James Kulp / Mercury Computer Systems, Inc. Abstract || Précis || Presentation - PDF | Précis || Poster - PPT |
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| Poster
B.3 |
An
Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs Tom Dillon / Dillon Engineering Abstract || Précis || Presentation - PDF | Précis || Poster - PPT |
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| Poster
B.4 |
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| Poster
B.5 |
Sparse
Linear Solver for Power System Analysis using FPGA Jeremy Johnson / Drexel University Prawaat Nagvajara / Drexel University Chika Nwankpa / Drexel University Abstract || Précis || Presentation - PDF | Précis || Poster - PPT |
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| Poster B.6 |
Initial
Kernel Timing Using a Simple PIM Performance Model |
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| Poster B.7 |
CASE
STUDY: Using Field Programmable Gate Arrays in a Beowulf Cluster |
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| Poster B.8 |
The
World's First Commercially-Available Stream Processor; Architecture,
Algorithms and Benchmark Results |
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| Poster B.9 |
High
Performance Embedded Computing using Field Programmable Gate Arrays |
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| Poster B.10 |
Dynamo:
A Runtime Codesign Environment |
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| Poster B.11 |
Hardware
Benchmark Results for An Ultra-High Performance Architecture for Embedded
Defense Signal and Image Processing Applications |
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| Poster B.12 |
Developing
Energy-Aware Strategies for the Blackfin Processor |
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| Session
4: Hardware Architecture Rick Pancoast / Lockheed Martin |
Focus
2: Parallel Software |
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| Microarchitecture
Optimization for Embedded Systems David Schuehler / Washington University Benjamin Brodie / Washington University Roger Chamberlain / Washington University Ron Cytron / Washington University Scott Friedman / Washington University Jason Fritts / Washington University Phillip Jones / Washington University Praveen Krishnamurthy / Washington University John Lockwood / Washington University Shobana Padmanabhan / Washington University Huakai Zhang / Washington University Abstract || Presentation - PDF | Presentation - PPT |
LLgrid:
Enabling On-Demand Grid Computing with gridMatlab and pMatlab |
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| Versatile
Tiled-Processor Architecture: The Raw Approach Rodric Rabbah / MIT Anant Agarwal / MIT Ian Bratt / MIT Abstract || Presentation - PDF | Presentation - PPT |
Parallel
Matlab Computation for STAP Clutter Scattering Function Estimation and
Moving Target Estimation |
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| Proposed
Parallel Architecture for Matrix Triangularization with Diagonal Loading Charles Rader / MIT Lincoln Laboratory Abstract || Presentation - PDF | Presentation - PPT |
Star-P:
High Productivity Parallel Computing |
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| Panel:
Amending Moore's Law for Embedded Applications Moderator: Dr. James C. Anderson / MIT Lincoln Laboratory - Presentation - PDF | Presentation - PPT Distinguished Panelists: - Mr. David Martinez / MIT Lincoln Laboratory - Presentation - PDF | Presentation - PPT - Dr. Richard Linderman / AFRL - Presentation - PDF | Presentation - PPT - Prof. Robert Schaller / College of Southern Maryland - Presentation - PDF | Presentation - PPT - Dr. Mark Richards / Georgia Institute of Technology - Presentation - PDF | Presentation - PPT |
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| 30 September |
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| Announcements |
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| From
a Federated to an Integrated Architecture for Dependable Embedded Systems
(Invited) |
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| Session
5: Standards Overview |
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| GPUs:
Engines for Future High-Performance Computing (Invited) |
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| OMG
Data-Distribution Service (DDS): Architectural Overview |
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| High
Productivity MPI - Grid, Multi-Cluster, and Embedded System Extensions |
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| HPEC
Related VITA Standards: An Update |
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| DigitalIF
Interface Standardization |
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| Poster
/ Demo C: Software |
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| Poster Session C Précis |
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| Poster C.1 |
An
Overview of the Common Component Architecture |
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| Poster C.2 |
Performance
Analysis of Real-Time CORBA on RapidIO |
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| Poster C.3 |
High-Assurance
Security/Safety on HPEC Systems: An Oxymoron? |
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| Poster C.4 |
Pulse
Compression Made Easy with VSIPL++ |
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| Poster C.5 |
Optimised
MPI for HPEC Applications |
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| Poster C.6 |
Implementing
the Matrix Exponential Function on Embedded Processors |
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| Poster C.7 |
R-Stream:
Compiler Technology for Next Generation HPEC |
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| Poster C.8 |
Utility
Accrual Scheduling of Distributable Threads: The Tempus Approach |
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| Poster C.9 |
Optimizing
the Fast Fourier Transform Over Memory Hierarchies for Embedded Digital
Systems: A Fully In-Cache Algorithm |
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| Poster C.10 |
Time-Frequency
Analysis for Single Channel Applications |
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| Poster C.11 |
Model
Driven Architectures and UML Performance Modeling Capability - Design
and Usage |
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| Focus
3: HPEC - Software Initiative |
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| VSIPL++:
Parallel Performance |
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| Evaluation
of the VSIPL++ Serial Specification using the DADS Beamformer |
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| Implementation
of a Shipboard Ballistic Missile Defense Processing Application using
the High Performance Embedded Computing Software Initiative (HPEC-SI)
API |
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| Adjourn |
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