HPEC 2009 Proceedings

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Note: Name of presenter is listed in italics.

22 September
Welcome
Mr. David Martinez / MIT Lincoln Laboratory
Presentation – PDF || Presentation – PPT
Mission Keynote: Technology’s Impact on Warfighting and Intelligence
Dr. Robert H. Latiff / Major General, USAF (RET)
Electronic files not available
Opening Remarks
Mr. Robert Bond / MIT Lincoln Laboratory
Presentation – PDF || Presentation – PPT

Session 1: HPC Landscape
Chair: Anthony Skjellum / University of Alabama at Birmingham
Auditorium
Presentation – PDF || Presentation – PPT

Focus 1: Space Technologies
Chair: Frank Pietryka / Raytheon Company
Room S2-180
Presentation – PDF || Presentation – PPT

Invited: Application Accelerators:
Deus ex machina?

Jeffrey Vetter / Oak Ridge National Laboratory and Georgia Institute of Technology
Presentation – PDF || Presentation – PPT

Invited: The Future of FPGAs
Rajit Manohar / Cornell University and Achronix Semiconductor Corp.
Presentation – PDF

Invited: Exascale Computing:
Embedded Style

Peter Kogge / University of Notre Dame
Presentation – PDF || Presentation – PPT

Invited: Bringing the Vision of Plug-and-play to High-Performance Computing on Orbit
James Lyke / AFRL
Presentation – PDF || Presentation – PPT

Invited: The Challenges of Cloud Computing
Dennis Gannon / Microsoft Research
Presentation – PDF || Presentation – PPT

High-performance Heterogeneous and Flexible Computing Architecture for Spacecraft Internet Protocol Communication and Payload
Ian Troxel, Steve Vaillancourt, Paul Murray and
Matthew Fehringer / SEAKR Engineering, Inc.
Abstract | Presentation – PDF || Presentation – PPT

Cloud Computing—Where ISR Data Will Go for Exploitation
Albert Reuther, Jeremy Kepner, Peter Michaleas and William Smith / MIT Lincoln Laboratory
Abstract | Presentation – PDF || Presentation – PPT

 

Poster / Demo A: Advanced Algorithms and Hardware
Chair: Anthony Skjellum / University of Alabama at Birmingham
Presentation – PDF || Presentation – PPT

Poster / Demo A Précis
Poster A.1 An Interactive Tool for Analyzing Kronecker Graphs
Huy Nguyen and Alan Edelman / Massachusetts Institute of Technology
Jeremy Kepner / MIT Lincoln Laboratory
Abstract | Précis – PDF || Précis – PPT
Poster A.2 Automated Parallelization of Non-uniform Convolutions on Chip Multiprocessors
Yuanrui Zhang and Mahmut Kandemir / Pennsylvania State University
Nikos Pitsianis and Xiaobai Sun / Duke University
Abstract | Précis – PDF || Précis – PPT
Poster A.3 Checking Model Specifications with CrossCheck
Jonathan Springer and James Ezick / Reservoir Labs, Inc.
Matthew Craven and Rick Buskens / Lockheed Martin
Abstract | Précis | Poster – PDF || Précis | Poster – PPT
Poster A.4 The PetaFlops Router: Harnessing FPGAs and Accelerators for High Performance Computing
Zachary Baker, Tanmoy Bhattacharya, Mark Dunham, Paul Graham, Rajan Gupta, Jeff Inman, Andreas Klein, Gerd Kunde, Al McPherson, Matt Stettler and Justin Tripp / Los Alamos National Laboratory
Abstract | Précis – PDF || Précis – PPT
Poster A.5 Modeling Singular Valued Decomposition (SVD) Techniques using the Parallel MATLAB Toolbox
Inerys Otero, Carlos González, Miguel Goenaga and Domingo Rodriguez / University of Puerto Rico
Abstract | Précis – PDF || Précis – PPT
Poster A.6 Thermal-Aware Scheduling for Real-Time Applications in Embedded Systems
Adam Lewis, Soumik Ghosh and Nian-Feng Tzeng / University of Louisiana at Lafayette
Abstract | Précis – PDF || Précis – PPT
Poster A.7 High-Speed Parallel Processing of Protocol-Aware Signatures
Jordi Ros-Giralt, James Ezick, Peter Szilagyi and Richard Lethin / Reservoir Labs, Inc.
Abstract | Précis | Poster – PDF || Précis – PPT
Poster A.8 UAV Video Image Stabilization on the SRC MAP Processor
William Turri / University of Dayton Research Institute
David Pointer / SRC Computers, LLC
Abstract | Précis – PDF || Précis – PPT
Poster A.9 Parallel Processing in ROSA II
Sara Siegal and Glenn Schrader / MIT Lincoln Laboratory
Abstract | Précis – PDF || Précis – PPT
Poster A.10 Dependable Multiprocessor (DM) Support for Diverse and Heterogeneous Processing
John Samson, Mathew Clark, Eric Grobelny and Susan Van Portfliiet / Honeywell Aerospace, Defense and Space Systems
Abstract | Précis – PDF || Précis – PPT
Poster A.11 Resource-aware Distributed Split Radix FFT on Wireless Sensor Networks
Sherine Abdelhak, Jared Tessier, Soumik Ghosh, Magdy Bayoumi and Nian-Feng Tzeng / University of Louisiana at Lafayette
Abstract | Précis – PDF || Précis – PPT
Poster A.12 High Bandwidth Data Collection and Processing Using OpenMPI on a LINUX Cluster
David MacPherson and Greg Kliss / SRC Inc.
Abstract
Poster A.13 Very High Level Languages (VHLL) for No Pain Scalable Computing on High Performance Systems
Bracy Elton, Siddharth Samsi, Harrison Ben Smith, Laura Humphrey, Stanley Ahalt and Alan Chalker / Ohio Supercomputer Center
Niraj Srivastava and Roope Astala / Interactive Supercomputing
Abstract | Précis | Poster – PDF || Précis | Poster – PPT
Poster A.14 Adapting the USRP as an Underwater Acoustic Modem
Paul Ozog, Miriam Leeser and Milica Stojanovic / Northeastern University
Abstract | Précis – PDF || Précis – PPT
   

Session 2: Decision Support
Chair: Nadya Bliss / MIT Lincoln Laboratory
Auditorium
Presentation – PDF || Presentation – PPT

Focus 2: Networks and Communications
Chair: Vladimir Stojanovic / Massachusetts Institute of Technology
Room S2-180
Presentation – PDF || Presentation – PPT

Invited: Cross-Domain ISR Maritime Awareness Demonstration
Kenneth Gregson / MIT Lincoln Laboratory
Presentation – PDF || Presentation – PPT

Silicon-Photonic Clos Networks for Global
On-Chip Communication

Ajay Joshi and Christopher Batten / Massachusetts Institute of Technology
Yong-Jin Kwon and Scott Beamer / University of California
Imran Shamim / Massachusetts Institute of Technology
Krste Asanovic / University of California
Vladimir Stojanovic / Massachusetts Institute of Technology
Abstract | Presentation – PDF || Presentation – PPT

Stochastic Digital Circuits for Probabilistic Inference
Vikash Mansinghka, Eric Jonas and Josh Tenenbaum / Massachusetts Institute of Technology
Electronic files not available

Photonic On-Chip Networks for Performance-Energy Optimized Off-Chip Memory Access
Gilbert Hendry, Daniel Brunina, Johnnie Chan, Luca Carloni and Keren Bergman / Columbia University
Abstract | Presentation – PDF || Presentation – PPT

Multi-objective Optimization of Sparse Array Computations
Una-May O’Reilly / Massachusetts Institute of Technology
Nadya Travinin Bliss, Sanjeev Mohindra, Julie Mullen and Eric Robinson / MIT Lincoln Laboratory
Abstract | Presentation – PDF || Presentation – PPT

Low Power Silicon Microphotonic Communications for Embedded Systems
Michael Watts, Anthony Lentine, Douglas Trotter, William Zortman, Ralph Young, David Campbell and Subhash Shinde / Sandia National Laboratories
Abstract | Presentation – PDF || Presentation – PPT

3D Exploitation of Large 2D Urban Photo Archives
Peter Cho and Ross Anderson / MIT Lincoln Laboratory
Noah Snavely / Cornell University
Abstract | Presentation – PDF || Presentation – PPT

A Special-Purpose Processor System with Software-Defined Connectivity
Benjamin Miller, Sara Siegal, James Haupt, Huy Nguyen and Michael Vai / MIT Lincoln Laboratory
Abstract | Presentation – PDF || Presentation – PPT

Optimizing an Innovative SAR Post-Processing Algorithm for Multi-Core Processors: A Case Study
Peter Carlston / Intel Corporation
Dave Murray / N.A. Software Ltd.
Abstract | Presentation – PDF || Presentation – PPT

OpenVPX: Architectures for High-Performance Embedded Computing
Robert Cooper / Mercury Computer Systems
Mark Littlefield / Curtiss-Wright Controls Embedded Computing
Abstract | Presentation – PDF || Presentation – PPT

Effective Floating Point Applications on FPGAs: Examples from Molecular Modeling
Bharat Sukhwani, Matt Chiu, Ashfaq Khan and Martin Herbordt / Boston University
Abstract | Presentation – PDF || Presentation – PPT

 
Closing Remarks / Adjourn
Jeremy Kepner / MIT Lincoln Laboratory
 
Reception and 2008 Awards  
Banquet Speaker:
Dr. Sigrid Close / Los Alamos National Laboratory
Electronic files not available
 
Banquet  
23 September
Announcements
Mr. Robert Bond / MIT Lincoln Laboratory

Technology Keynote: Air Force Science and Technology Issues and Opportunities Regarding High Performance Embedded Computing
Dr. Richard Linderman / AFRL
Presentation – PDF || Presentation – PPT

Session 3: GPU
Chair: James Lebak / Mathworks
Auditorium
Presentation – PDF || Presentation – PPT

Focus 3: Multicore Programming
Chair: Craig Lund / Local Knowledge
Room S2-180
Presentation – PDF || Presentation – PPT

Invited: Data Intensive Computing on Heterogeneous Platforms
Norman Rubin / Advanced Micro Devices, Inc.
Presentation – PDF || Presentation – PPT

High Performance Linear Transform Program Generation for the Cell BE
Srinivas Chellappa, Franz Franchetti and Markus Püschel / Carnegie Mellon University
Abstract | Presentation – PDF || Presentation – PPT

Fast Pattern Matching in 3D Images on GPUs
Patrick Eibl and Dennis Healy / Duke University
Nikos Pitsianis / Duke University / Aristotle University
Xiaobai Sun / Duke University
Abstract | Presentation – PDF || Presentation – PPT

Implementation of 2-D FFT on the Cell Broadband Engine Architecture
Kerry Barnes, William Lundgren and James Steed / Gedae, Inc.
Abstract | Presentation – PDF || Presentation – PPT

Hierarchical Parallelization of a Radio Frequency Tomography Application via Multiple GPUs
Dana Schaa / Northeastern University
Mark Barnell / AFRL
Roope Astala, Steve Reinhardt and Viral Shah /
Interactive Supercomputing
Abstract | Presentation – PDF || Presentation – PPT

Remote Store Programming: Reflective Memory for Multicore
Henry Hoffmann, David Wentzlaff and Anant Agarwal / Massachusetts Institute of Technology
Abstract | Presentation – PDF || Presentation – PPT

GPU Accelerated Decoding of High Performance Error Correcting Codes
Andrew Copeland, Nicholas Chang and Stephen Leung / MIT Lincoln Laboratory
Abstract | Presentation – PDF || Presentation – PPT

A Multi-Paradigm Programming Model for Heterogeneous Architectures
Michael Champigny / Mercury Computer Systems
Abstract | Presentation – PDF || Presentation – PPT

Accelerating a MATLAB Application with Nvidia GPUs: a Case Study for GPU Library Construction
Nicholas Moore and Miriam Leeser / Northeastern University
Abstract | Presentation – PDF

Runtime Verification and Validation for Multi-Core Based On-Board Computing
Hans Zima and Mark James / Jet Propulsion Laboratory
Abstract | Presentation – PDF || Presentation – PPT

 

The “State” and “Future” of Middleware for HPEC
Anthony Skjellum / RunTime Computing Solutions, LLC and University of Alabama at Birmingham
Abstract | Presentation – PDF || Presentation – PPT

Poster / Demo B: FPGA Technologies and Applications
Chair: James Lebak / Mathworks
Presentation – PDF || Presentation – PPT

Poster / Demo B Précis
Poster B.1 Signal/Data Processor Implementation and Algorithms for Realtime Wide-Angle Ultra-Wideband SAR Image Formation
Jeff Isenman and Eric Jones / Lockheed Martin IS&GS
David Caliga / SRC Computers, LLC
Abstract | Précis – PDF || Précis – PPT
Poster B.2 GPU VSIPL: Core and Beyond
Andrew Kerr, Dan Campbell and Mark Richards / Georgia Institute of Technology
Abstract | Précis – PDF || Précis – PPT
Poster B.3 RAPID—A Rapid Prototyping Methodology for Embedded Systems
Huy Nguyen, Michael Vai, Andrew Heckerling, Michael Eskowitz, Ford Ennis, Thomas Anderson, Larry Retherford and George Lambert / MIT Lincoln Laboratory
Abstract | Précis – PDF || Précis – PPT
Poster B.4 Floating Point Synthesis from Model-Based Design
Mark Jervis, Martin Langhammer, Mark Santoro and Graham Griffiths / Altera Europe
Abstract | Précis | Poster – PDF || Précis | Poster – PPT
Poster B.5 Heterogeneous Processing Solutions for the IBM BladeCenter
Patrick Stover and Paul Letourneau / Annapolis Micro Systems
Abstract | Précis – PDF || Précis – PPT
Poster B.6 Disruptive Applications of GPGPU Technology
Matthew Curry and Anthony Skjellum / University of Alabama at Birmingham
Abstract | Précis – PDF || Précis – PPT
Poster B.7 Performance of Graph and Biological Analytics on the Cell Broadband Engine Processor
Tan Tran and David Bader / Georgia Institute of Technology
Précis | Poster – PDF || Précis | Poster – PPT
Poster B.8 DAPR: Design Automation for Partially Reconfigurable FPGAs
Shaon Yousuf and Ann Gordon-Ross / NSF Center for High-Performance Reconfigurable Computing (CHREC)
Electronic files not available
Poster B.9 A Fault Tolerant Gaussian Elimination Solver for the Cell Broadband Engine
James Geraci / Square-Enix Research and Development
Abstract | Précis | Poster – PDF || Précis | Poster – PPT
Poster B.10 QR Decomposition: Demonstration of Distributed Computing on Wireless Sensor Networks
Sherine Abdelhak, Soumik Ghosh, Rabi Chaudhuri and Magdy Bayoumi / University of Louisiana at Lafayette
Abstract | Précis – PDF || Précis – PPT
Poster B.11 Developing Fast DSP Libraries for Advanced Processors
David Murray and Mike Delves / N.A. Software Ltd.
Abstract | Précis – PDF || Précis – PPT
Poster B.12 Kronecker Products-based Regularized Image Interpolation Techniques
Blas Trigueros, Ricardo Castañeyra and Domingo Rodriguez / University of Puerto Rico
Abstract | Précis – PDF || Précis – PPT
Session 4: Awards Session
Chair: Jeremy Kepner / MIT Lincoln Laboratory
Auditorium
Presentation – PDF || Presentation – PPT
*Nonlinear Equalization Processor IC for Wideband Receivers and Sensors
William Song, Joshua Kramer, James Mann, Karen Gettings, Joel Goodman, Benjamin Miller, Matthew Herman, Thomas Emberley, Larry Retherford and Albert Horst / MIT Lincoln Laboratory
Gil Raz / GMR Research & Technology, Inc.
Abstract | Presentation – PDF || Presentation – PPT
*Sourcery VSIPL++ for NVIDIA CUDA GPUs
Don McCoy, Brooks Moses, Stefan Seefeld, Mike LeBlanc and Jules Bergmann / CodeSourcery, Inc.
Abstract | Presentation – PDF || Presentation – PPT
*Automatic Generation of Vectorized FastFourier Transform Libraries for the Larrabee and AVX Instruction SetExtension
Daniel McFarlin, Franz Franchetti and Markus Püschel / Carnegie Mellon University
Abstract | Presentation – PDF || Presentation – PPT

Panel: Survivor: Computer Architecture
Moderator: Dr. Richard Linderman / AFRL
Presentation – PDF || Presentation – PPT

Distinguished Panelists:
Prof. Rajit Manohar / Cornell University and Achronix Semiconductor Corporation
Mr. Andreas Olofsson / Adapteva, Inc.
Dr. Norman Rubin / Advanced Micro Devices, Inc.
Dr. David Scott / Intel Corporation

IARPA and Its Mission
Edward Baranoski / IARPA
Presentation – PDF || Presentation – PPT

Closing Remarks / Adjourn
*Outstanding Submission