HPEC 2004 Preliminary Agenda

Check-In / Poster Setup / Continental Breakfast

Welcome
David Martinez / MIT Lincoln Laboratory

Opening Remarks
Robert Bond / MIT Lincoln Laboratory

Session 1: Emerging Technologies
Kenneth Teitelbaum / MIT Lincoln Laboratories

Cognitive Systems (Invited)
Robert Graybill / DARPA IPTO

Future Prospects for Moore's Law (Invited)
Robert Doering / Texas Instruments

The Evaluation of GPU-Based Programming Environments for Knowledge Discovery
John Johnson / Lawrence Livermore National Library
Randall Frank / Lawrence Livermore National Library
Sheila Vaidya / Lawrence Livermore National Library

Sustaining the Exponential Growth of Embedded Digital Signal Processing Capability
Gary Shaw / MIT Lincoln Laboratory
Mark Richards / Georgia Institute of Technology

Poster / Demo A: High Level Environments and Interconnects
Albert Reuther / Lincoln Laboratory

Poster Session A Précis

Application-Specific Optical Interconnects for Embedded Multiprocessors
Neal Bambha / U.S. Army Research Lab
Shuvra Bhattacharyya / University of Maryland, College Park

Software Architecture for Morphing in Polymorphous Computing Architectures
Dan Campbell / Georgia Institute of Technology
Dennis Cottel / SPAWAR Systems Center
Randall Judd / SPAWAR Systems Center
Mark Richards / Georgia Institute of Technology

Parallel Matlab: RTExpress on 64-bit SGI Altix with SCSL and MPT
Cosmo Castellano / Integrated Sensors

pMatlab Takes the HPCchallenge
Ryan Haney / MIT Lincoln Laboratory
Andrew Funk / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Hahn Kim / MIT Lincoln Laboratory
Charles Rader / MIT Lincoln Laboratory
Albert Reuther / MIT Lincoln Laboratory
Nadya Travinin / MIT Lincoln Laboratory

Gedae: Auto Coding to a Virtual Machine
William Lundgren / Gedae, Inc.
Kerry Barnes / Gedae, Inc.
James Steed / Blue Horizon Development Software

Requirements for Scalable Application Specific Processing in Commercial HPEC
Steve Miller / Silicon Graphics, Inc.

Implementing Modal Software in Data Flow for Heterogeneous Architectures
James Steed / Gedae, Inc.
Kerry Barnes / Gedae, Inc.
William Lundgren / Gedae, Inc.

The Development of a Tactical Environmental Processor (TEP) Open Architecture (OA) Application Using Middleware Standard APIs
Bonnie Vena / Lockheed Martin MS&S
Carl Barberi / Lockheed Martin MS&S
Steve Paavola / SKY Computers, Inc.

Lunch (View Posters)

Session 2: Novel Systems
Michael Harris / BAE Space Systems IEWS
Auditorium

Deployment of SAR and GMTI Signal Processing on a Boeing 707 Aircraft using pMatlab and a Bladed Linux Cluster
Jeremy Kepner / MIT Lincoln Laboratory
Tim Currie / MIT Lincoln Laboratory
Hahn Kim / MIT Lincoln Laboratory
Bipin Mathew / MIT Lincoln Laboratory
Andrew McCabe / MIT Lincoln Laboratory
Michael Moore / MIT Lincoln Laboratory
Daniel Rabinkin / MIT Lincoln Laboratory
Albert Reuther / MIT Lincoln Laboratory
Andrew Rhoades / MIT Lincoln Laboratory
Louis Tella / MIT Lincoln Laboratory
Nadya Travinin / / MIT Lincoln Laboratory

Virtual Prototyping and Performance Analysis of RapidIO-based System Architectures for Space-Based Radar
David Bueno / University of Florida
Chris Conger / University of Florida
Alan George / University of Florida
Adam Leko / University of Florida
Ian Troxel / University of Florida

Kronecker-FFT Algorithms for Multidimensional SAR PSF Processing
Domingo Rodriquez / University of Puerto Rico

Break (View Posters)

A KASSPER Real-Time Signal Processor Testbed
Glen Schrader / MIT Lincoln Laboratory

HPCS HPCchallenge Benchmark Suite
David Koester / The MITRE Corporation
Jack Dongarra / University of Tennessee
Piotr Luszczek / Innovative Computing Laboratory

Banquet Presentation
Title: TBD
Dr. Michael Flynn / Stanford University

Banquet (Burlington Marriott)

Check-In / Poster Setup / Continental Breakfast

Announcements
Robert Bond / MIT Lincoln Laboratory

Session 3: FPGAs
John Grosh / OSD

Microprocessor Design Tradeoffs (Invited)
H. Peter Hofstee / IBM

FPGA Acceleration of Information Management Services
Richard Linderman / AFRL
Chun-Shin Lin / University of Missouri, Columbia
Mark Linderman / AFRL

Break (View Posters)

A Systolic FFT Architecture for Real Time FPGA Systems
Preston Jackson / MIT Lincoln Laboratory
Cy Chan / MIT Lincoln Laboratory
Charles Rader / MIT Lincoln Laboratory
Jonathan Scalera / MIT Lincoln Laboratory
Michael Vai / MIT Lincoln Laboratory

Variable Precision Floating Point Division and Square Root
Miriam Leeser / Northeastern University
Xiaojun Wang / Northeastern University
Albert Conti / Norhteastern University

Poster / Demo B: Dynamic Hardware
Michael Vai / MIT Lincoln Laboratory

Poster Session B Précis

Automated Incremental Design of Flexible Instrusion Detection Systems on FPGAs
Zachary Baker / University of Southern California
Viktor Prasanna / University of Southern California
Ronald Scrofano / University of Southern California

Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components
Graham Bardouleau / Mercury Computer Systems, Inc.
James Kulp / Mercury Computer Systems, Inc.

An Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs
Tom Dillon / Dillon Engineering

MONARCH: Next Generation SoC (Super Computer on a Chip)
John Granacki / University of Southern California

Sparse Linear Solver for Power System Analysis using FPGA
Jeremy Johnson / Drexel University
Prawaat Nagvajara / Drexel University
Chika Nwankpa / Drexel University

Lunch (View Posters)

Session 4: Hardware Architecture
Rick Pancoast / Lockheed Martin
Auditorium

Microarchitecture Optimization for Embedded Systems
David Schuehler / Washington University
Benjamin Brodie / Washington University
Roger Chamberlain / Washington University
Ron Cytron / Washington University
Scott Friedman / Washington University
Jason Fritts / Washington University
Phillip Jones / Washington University
Praveen Krishnamurthy / Washington University
John Lockwood / Washington University
Shobana Padmanabhan / Washington University
Huakai Zhang / Washington University

Versatile Tiled-Processor Architecture: The Raw Approach
Rodric Rabbah / MIT CSAIL
Anant Agarwal / MIT CSAIL
Ian Bratt / MIT CSAIL
Krste Asanovic / MIT CSAIL

Proposed Parallel Architecture for Matrix Triangularization with Diagonal Loading
Charles Rader / MIT Lincoln Laboratory

Break (View Posters)

Panel: Amending Moore's Law for Embedded Applications
Moderator:
Dr. James C. Anderson / MIT Lincoln Laboratory
Distinguished Panelists:
Mr. David Martinez / MIT Lincoln Laboratory
Dr. Richard Linderman / AFRL
Dr. Robert Schaller / College of Southern Maryland
Dr. Mark Richards / Georgia Institute of Technology

HPEC 2004 Preliminary Agenda - pdf version
*Denotes outstanding submission

28 September

0730		Check-In / Poster Setup / Continental Breakfast

AUDITORIUM

0830		Welcome David Martinez / MIT Lincoln Laboratory

0835		Opening Remarks Robert Bond / MIT Lincoln Laboratory

0845		Supercomputing: Trends, Performance Measurement and Opportunities (Invited) Cray Henry / High Performance Computing Modernization Program

0915		Session 1: Emerging Technologies Kenneth Teitelbaum / MIT Lincoln Laboratories

0925		Cognitive Systems (Invited) Robert Graybill / DARPA IPTO

0955		Future Prospects for Moore's Law (Invited) Robert Doering / Texas Instruments

1025		Break (View Posters)

1040		The Evaluation of GPU-Based Programming Environments for Knowledge Discovery John Johnson / Lawrence Livermore National Library Randall Frank / Lawrence Livermore National Library Sheila Vaidya / Lawrence Livermore National Library

1110		Sustaining the Exponential Growth of Embedded Digital Signal Processing Capability Gary Shaw / MIT Lincoln Laboratory Mark Richards / Georgia Institute of Technology

1140		Poster / Demo A: High Level Environments and Interconnects Albert Reuther / Lincoln Laboratory

Poster Session A Précis

Poster A.1		Application-Specific Optical Interconnects for Embedded Multiprocessors Neal Bambha / U.S. Army Research Lab Shuvra Bhattacharyya / University of Maryland, College Park

Poster A.2		Software Architecture for Morphing in Polymorphous Computing Architectures Dan Campbell / Georgia Institute of Technology Dennis Cottel / SPAWAR Systems Center Randall Judd / SPAWAR Systems Center Mark Richards / Georgia Institute of Technology

Poster A.3		Parallel Matlab: RTExpress on 64-bit SGI Altix with SCSL and MPT Cosmo Castellano / Integrated Sensors

Poster A.4		pMatlab Takes the HPCchallenge Ryan Haney / MIT Lincoln Laboratory Andrew Funk / MIT Lincoln Laboratory Jeremy Kepner / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Charles Rader / MIT Lincoln Laboratory Albert Reuther / MIT Lincoln Laboratory Nadya Travinin / MIT Lincoln Laboratory

Poster A.5		Gedae: Auto Coding to a Virtual Machine William Lundgren / Gedae, Inc. Kerry Barnes / Gedae, Inc. James Steed / Blue Horizon Development Software

Poster A.6		Requirements for Scalable Application Specific Processing in Commercial HPEC Steve Miller / Silicon Graphics, Inc.

Poster A.7		Benchmarking Microprocessors for High-End Signal Processing Stephen Paavola / SKY Computers

Poster A.8		Processing Challenges in Shrinking HPEC Systems into Small UAVs Stephen Pearce / Mercury Computer Systems, Inc. Richard Jaenicke / Mercury Computer Systems, Inc.

Poster A.9		Implementing Modal Software in Data Flow for Heterogeneous Architectures James Steed / Gedae, Inc. Kerry Barnes / Gedae, Inc. William Lundgren / Gedae, Inc.

Poster A.10		The Development of a Tactical Environmental Processor (TEP) Open Architecture (OA) Application Using Middleware Standard APIs Bonnie Vena / Lockheed Martin MS&S Carl Barberi / Lockheed Martin MS&S Steve Paavola / SKY Computers, Inc.


1235		Lunch (View Posters)

1345		Session 2: Novel Systems Michael Harris / BAE Space Systems IEWS Auditorium	Focus 1: Advanced Software Optimization David Cousins / BBN Technolgoies Room S2-180

1355	*	Deployment of SAR and GMTI Signal Processing on a Boeing 707 Aircraft using pMatlab and a Bladed Linux Cluster Jeremy Kepner / MIT Lincoln Laboratory Tim Currie / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Bipin Mathew / MIT Lincoln Laboratory Andrew McCabe / MIT Lincoln Laboratory Michael Moore / MIT Lincoln Laboratory Daniel Rabinkin / MIT Lincoln Laboratory Albert Reuther / MIT Lincoln Laboratory Andrew Rhoades / MIT Lincoln Laboratory Louis Tella / MIT Lincoln Laboratory Nadya Travinin / / MIT Lincoln Laboratory	Discrete Fourier Transform IP Generator Grace Nordin / Carnegie Mellon University James Hoe / Carnegie Mellon University Markus Pueschel / Carnegie Mellon University

1425		Virtual Prototyping and Performance Analysis of RapidIO-based System Architectures for Space-Based Radar David Bueno / University of Florida Chris Conger / University of Florida Alan George / University of Florida Adam Leko / University of Florida Ian Troxel / University of Florida	Mapping Signal Processing Kernels to Tiled Architectures Henry Hoffman / MIT Lincoln Laboratory James Lebak / MIT Lincoln Laboratory

1455		Kronecker-FFT Algorithms for Multidimensional SAR PSF Processing Domingo Rodriquez / University of Puerto Rico	A Transformational Approach to High Performance Embedded Computing Wim Bohm / Colorado State University Jeff Hammes / SRC Computers, Inc.

1525		Break (View Posters)	Break

1550		A KASSPER Real-Time Signal Processor Testbed Glen Schrader / MIT Lincoln Laboratory	Adaptive Mapping of Linear DSP Algorithms to Fixed-Point Arithmetic Lawrence Chang / Carnegie Mellon University Markus Pueschel / Carnegie Mellon University Yevgen Voronenko / Carnegie Mellon University Inpyo Hong / Carnegie Mellon University

1620		HPCS HPCchallenge Benchmark Suite David Koester / The MITRE Corporation Jack Dongarra / University of Tennessee Piotr Luszczek / Innovative Computing Laboratory	Language-level Transactions for Modular Reliable Systems C. Scott Ananian / MIT CSAIL Martin Rinard / MIT CSAIL

1650		Title: TBD (Invited) Mootaz Elnozahy / IBM Austin Research Lab	SAE AADL: An Industry Standard for Predictable Embedded Real-Time Systems Engineering Peter Feiler / Carnegie Mellon University

1720		Adjourn

1730		Reception

1800		Banquet Presentation Title: TBD Dr. Michael Flynn / Stanford University

1845		Banquet (Burlington Marriott)

29 September

0730		Check-In / Poster Setup / Continental Breakfast


0830		Announcements Robert Bond / MIT Lincoln Laboratory

0835		Keynote Address Title: Why Latency Lags Bandwidth, and What it Means to Computing Dr. David Patterson / University of California, Berkeley

0905		Session 3: FPGAs John Grosh / OSD

0915		Microprocessor Design Tradeoffs (Invited) H. Peter Hofstee / IBM

0945		FPGA Acceleration of Information Management Services Richard Linderman / AFRL Chun-Shin Lin / University of Missouri, Columbia Mark Linderman / AFRL

1015		Break (View Posters)

1030		A Systolic FFT Architecture for Real Time FPGA Systems Preston Jackson / MIT Lincoln Laboratory Cy Chan / MIT Lincoln Laboratory Charles Rader / MIT Lincoln Laboratory Jonathan Scalera / MIT Lincoln Laboratory Michael Vai / MIT Lincoln Laboratory

1100		Variable Precision Floating Point Division and Square Root Miriam Leeser / Northeastern University Xiaojun Wang / Northeastern University Albert Conti / Norhteastern University

1130		Poster / Demo B: Dynamic Hardware Michael Vai / MIT Lincoln Laboratory

Poster Session B Précis

Poster B.1		Automated Incremental Design of Flexible Instrusion Detection Systems on FPGAs Zachary Baker / University of Southern California Viktor Prasanna / University of Southern California Ronald Scrofano / University of Southern California

Poster B.2		Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components Graham Bardouleau / Mercury Computer Systems, Inc. James Kulp / Mercury Computer Systems, Inc.

Poster B.3		An Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs Tom Dillon / Dillon Engineering

Poster B.4		MONARCH: Next Generation SoC (Super Computer on a Chip) John Granacki / University of Southern California

Poster B.5		Sparse Linear Solver for Power System Analysis using FPGA Jeremy Johnson / Drexel University Prawaat Nagvajara / Drexel University Chika Nwankpa / Drexel University

Poster B.6		Initial Kernel Timing Using a Simple PIM Performance Model Daniel Katz / Jet Propulsion Laboratory Gary Block / Jet Propulsion Laboratory Jay Brockman / University of Notre Dame David Callahan / Cray, Inc. Paul Springer / Jet Propulsion Laboratory Thomas Sterling / Center for Advanced Computing Research

Poster B.7		CASE STUDY: Using Field Programmable Gate Arrays in a Beowulf Cluster Matthew Krzych / NUWC

Poster B.8		The World's First Commercially-Available Stream Processor: Architecture, Algorithms and Benchmark Results Simon McIntosh-Smith / ClearSpeed Technology Ron Bell / AWE Aldermaston

Poster B.9		High Performance Embedded Computing using Field Programmable Gate Arrays Craig Petrie / Nallatech, Ltd. Charlie Cump / Nallatech, Ltd. Malachy Devlin / Nallatech, Ltd. Keith Regester / Nallatech, Inc.

Poster B.10		Dynamo: A Runtime Codesign Environment Heather Quinn / Northeastern University Laurie King / College of the Holy Cross Miriam Leeser / Northeastern University

Poster B.11		Hardware Benchmark Results for An Ultra-High Performance Architecture for Embedded Defense Signal and Image Processing Applications Stewart Reddaway / WorldScape Defense Co. Brad Atwater / Lockheed Martin MS&S Paul Bruno / WorldScape Defense Co. Dairsie Latimer / ClearSpeed Technology, Ltd. Rick Pancoast / Lockheed Martin NE&SS Pete Rogina / WorldScape, Inc.

Poster B.12		Developing Energy-Aware Strategies for the Blackfin Processor Steven VanderSanden / Northeastern University Richard Gentile / Analog Devices, Inc. David Kaeli / Northeastern University Giuseppe Olivadoti / Analog Devices, Inc.

1225		Lunch (View Posters)

1335		Session 4: Hardware Architecture Rick Pancoast / Lockheed Martin Auditorium	Focus 2: Parallel Software Cleve Moler / The MathWorks, Inc. Room S2-180

1345		Microarchitecture Optimization for Embedded Systems David Schuehler / Washington University Benjamin Brodie / Washington University Roger Chamberlain / Washington University Ron Cytron / Washington University Scott Friedman / Washington University Jason Fritts / Washington University Phillip Jones / Washington University Praveen Krishnamurthy / Washington University John Lockwood / Washington University Shobana Padmanabhan / Washington University Huakai Zhang / Washington University	LLgrid: Enabling On-Demand Grid Computing with gridMatlab and pMatlab Albert Reuther / MIT Lincoln Laboratory Tim Currie / MIT Lincoln Laboratory Jeremy Kepner / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Andrew McCabe / MIT Lincoln Laboratory Michael Moore / MIT Lincoln Laboratory Nadya Travinin / MIT Lincoln Laboratory

1415		Versatile Tiled-Processor Architecture: The Raw Approach Rodric Rabbah / MIT CSAIL Anant Agarwal / MIT CSAIL Ian Bratt / MIT CSAIL Krste Asanovic / MIT CSAIL	Parallel Matlab Computation for STAP Clutter Scattering Function Estimation and Moving Target Estimation Roger Chamberlain / Washington University Lisandro Boggio / Washington University Daniel Fuhrmann / Washington University John Maschmeyer / Washington University

1445		Proposed Parallel Architecture for Matrix Triangularization with Diagonal Loading Charles Rader / MIT Lincoln Laboratory	Star-P: High Productivity Parallel Computing Ron Choy / CSAIL, MIT David Cheng / CSAIL, MIT Alan Edelman / CSAIL, MIT John Gilbert / University of California, Santa Barbara Viral Shah / University of California, Santa Barbara

1515		Break (View Posters)

1540		Panel: Amending Moore's Law for Embedded Applications Moderator: Dr. James C. Anderson / MIT Lincoln Laboratory Distinguished Panelists: Mr. David Martinez / MIT Lincoln Laboratory Dr. Richard Linderman / AFRL Dr. Robert Schaller / College of Southern Maryland Dr. Mark Richards / Georgia Institute of Technology

1730		Adjourn

30 September

0730		Check-In / Poster Setup / Continental Breakfast

0830		Announcements Robert Bond / MIT Lincoln Laboratory

0835		From a Federated to an Integrated Architecture for Dependable Embedded Systems (Invited) Dr. Hermann Kopetz / Institut fur Technnische Informatik

0905		Session 5: Standards Overview Craig Lund / Mercury Computer Systems, Inc.

0920		GPUs: Engines for Future High-Performance Computing (Invited) John Owens / University of California at Davis

0945		OMG Data-Distribution Service (DDS): Architectural Overview Gerardo Pardo-Castellote / Real-Time Innovations

1010		High Productivity MPI - Grid, Multi-Cluster, and Embedded System Extensions Pirabbhu Raman / Verari Systems Software, Inc. Puri Banglore / Verari Systems Software, Inc. Rossen Dimitrov / Verari Systems Software, Inc. Kumaran Rajaram / Verari Systems Software, Inc. Anthony Skjellum / Verari Systems Software, Inc.

1035		Break (View Posters)

1055		HPEC Related VITA Standards: An Update Randy Banton / Mercury Computers

1110		DigitalIF Interface Standardization Paul Mesibov / Pentek

1125		Poster / Demo C: Software Stephen Paavola / SKY Computers, Inc.

Poster Session C Précis

Poster C.1		An Overview of the Common Component Architecture Rob Armstrong / Sandia National Laboratory David Bernholdt / Oak Ridge National Laboratory Teresa Ko / Sandia National Laboratory

Poster C.2		Performance Analysis of Real-Time CORBA on RapidIO Bill Beckwith / Objective Interface Systems, Inc. Kevin Buesing / Objective Interface Systems, Inc.

Poster C.3		High-Assurance Security/Safety on HPEC Systems: An Oxymoron? Bill Beckwith / Objective Interface Systems, Inc. Mark Vanfleet / National Security Agency

Poster C.4		Pulse Compression Made Easy with VSIPL++ Brian Chase / Verari Systems Software Dave Leimbach / Verari Systems Software Rick Pancoast / Lockheed Martin NE&SS Anthony Skjellum / Verari Systems Software Wenhao Wu / Verari Systems Software

Poster C.5		Optimised MPI for HPEC Applications Gerard Cristau / Thales Computers Vincent Chuffart / Thales Computers

Poster C.6		Implementing the Matrix Exponential Function on Embedded Processors James Lebak / MIT Lincoln Laboratory Andrea Wadell / MIT Lincoln Laboratory

Poster C.7		R-Stream: Compiler Technology for Next Generation HPEC Richard Lethin / Reservoir Labs, Inc. Peter Mattson / Reservoir Labs, Inc.

Poster C.8		Utility Accrual Scheduling of Distributable Threads: The Tempus Approach Peng Li / Virginia Polytechnic Institute E. Douglas Jensen / The MITRE Corporation Binoy Ravindran / Virginia Polytechnic Institute

Poster C.9		Optimizing the Fast Fourier Transform Over Memory Hierarchies for Embedded Digital Systems: A Fully In-Cache Algorithm James Reynolds / SUNY, Albany Lenore Mullin / SUNY, Albany

Poster C.10		Time-Frequency Analysis for Single Channel Applications John Saunders / Mercury Computers

Poster C.11		Model Driven Architectures and UML Performance Modeling Capability - Design and Usage Leonard Weinberg / Lockheed Martin MS&S Harald Pschunder / Lockheed Martin MS&S Michael Stebnisky / Lockheed Martin ATL

1220		Lunch (View Posters)

1330		Session 6: Advanced Systems Henk Spaanenburg / Pentum Group Auditorium: Closed / Limited	Focus 3: HPEC-Software Initiative Jeremy Kepner / MIT Lincoln Laboratory Room S2-180: Open / Public Domain

			1340	VSIPL++: Parallel Performance Mark Mitchell / CodeSourcery, LLC Jeffrey Oldham / CodeSourcery, LLC

			1410	Evaluation of the VSIPL++ Serial Specification Using the DADS Beamformer Dennis Cottell / SPAWAR Systems Center Randall Judd / SPAWAR Systems Center

			1440	Implementation of a Shipboard Ballistic Missile Defense Processing Application Using the High Performance Embedded Computing Software Initiative (HPEC-SI) API Joe Cook / Lockheed Martin NE&SS Nathan Doss / Lockheed Martin NE&SS Jane Kent / Lockheed Martin NE&SS Jeremy Kepner / MIT Lincoln Laboratory Rick Pancoast / Lockheed Martin NE&SS

			1510	Adjourn - Open/Public Domain Session
1705		Adjourn - Closed/Limited Session