MIT Lincoln Laboratory

HPEC 1997
17-18 September 1997


Check-In & Continental Breakfast
Keynote Address
Fifty Years of Navy Embedded Computing
RADM Kathleen Paige (U.S. Navy / NSWC)
Session 1:  Embedded Systems Applications
Glenn Ladd ( Hughes Aircraft Company)
Parallel Processing Developement Needs for Foliage Penetration (FOPEN) Radar
Mark Davis (DARPA/ISO)
Dave Kirk (Decision-Science Applications)
Paul Maloney (Decision-Science Applications)
Paralell Processing of Airborne UHF/VHF Ultra-Wideband Synthetic Aperature Radar Data
Matthew Braunstein (MIT Lincoln Laboratory)
David Payne (Intel Corporation)
Thanh Phung (Intel Corporation)
Massively Parallel Processing COTS Hardware for Future Advanced Aperature AEGIS Signal Processor
James Lebak (MIT Lincoln Laboratory
Edward Baranoski (MIT Lincoln Laboratory)
Performance Modeling and Simulation for AEGIS Signal Processor Upgrade
Chad Hawes (Lockheed Martin, Government Electronic Systems)
Rathin Putatunda (Lockheed Martin, Government Electronic Systems)
Poster Session A:  Prototyping Tools and Compilers
Henk Spaanenburg ( Lockheed Sanders)

Poster A.1 Data Parallel C for the SHARC
Michael Collision (ISIS Associates, Inc.) 
Poster A.2 Bridging the Development Gap
Arlan Pool (Mercury Computer Systems)
Richard Drohan (The MathWorks)
Poster A.3 Automatic Implementation of High-Performance Multidimensional and Dimensionless FFTs
Louis Auslander (City University of NY)
Jeremy Johnson(Drexel University)
Robert Johnson (St. Cloud State University)
Poster A.4 Case Study of a RCC Embedded System Using Lab Windows CVI
John Layne (Los Alamos National Laboratory)
Anthony Salazar (Los Alamos National Laboratory)
Poster A.5 Graphical Programming and Autocoding for Multiprocessor Systems
William Lundgren (Lockheed Martin, Advanced Technology Laboratory)
Poster A.6    Compiling for Heterogeneous Embedded Systems
Kathryn McKinley (University of Massachusetts)
Glen Weaver (University of Massachusetts)
Charles Weems (University of Massachusetts)
Poster A.7 RCSP: A Parameterized Reduced Configuration Space Processor and its Programming Environment
Krishna Palem (Courant Inst. of Mathematical Sciences)
Surendranath Talla (Courant Inst. of Mathematical Sciences)
Session 2:  Case Studies of System Implementations
Robert Bernecky (Naval Undersea Warfare Center)
A Distributed Parallel Embedded System for Autonomous Sonar Arrays 
Warren Rosen (Drexel University)
Alan George ( University of Florida)
Implementation of a Real-Time Parallel Processing System
David Carney (Software Engineering Institute)
Evaluating Commercial Products for Use in Complex Software Systems
David Carney (Software Engineering Institute)
Lessons Learned in Performance Characterization of COTS Real-Time Computing Systems
Jamie Durbin (Lockheed Martin, Government Electronic Systems)
Jim Briggs (Lockheed Martin, Government Electronic Systems)
Christine Cargado (Lockheed Martin, Government Electronic Systems)
Session 3:  Scalable Architectures and Algorithm Mappings
Robert Bond (MIT Lincoln Laboratory)
Scalability of Crossbar Tree Architectures
Kenneth Teitebaum (MIT Lincoln Laboratory)
Mapping Analysis of Advanced Adaptive Processing on a Parallel Architecture
Janice Onanian McMahon (MIT Lincoln Laboratory)
Matthew Sexton (Mercury Computer Systems)
Space-Time Adaptive Processing Using a High-Performance Scalable Computer
Ronald Hamlet (Lockheed Martin OR&SS)
Check-In & Continental Breakfast
Session 4:   Standardization for Embedded Systems
Eric Pancoast (Lockheed Martin)
Tactical Advanced Signal Processor (TASP) Program
Tim Singleton (U.S. Navy / PMS 428)
VSIP: A Standard API for Vector Signal and Image Processing
David Schwartz (Hughes Research Laboratory)
Design and Development of the Real-Time Message Passing Interference (MPI/RT) Standard
Anthony Skjellum (Mississippi State  University)
Arkady Kanevsky (MITRE)
Embedded Software  Standards
Craig Lund (Mercury Computer Systems)
Session 5:  Software Portability
Viktor Prasanna (University of Southern California)
A Portable and Reuseable Object-Based Parallel Library and Layered Framework for Real-Time Embedded Radar Signal Processing
Cecelia DeLuca (MIT Lincoln Laboratory)
Curtis Heisey (MIT Lincoln Laboratory)
Robert Bond (MIT Lincoln Laboratory)
James Daly (MIT Lincoln Laboratory)
Poster Session B:  Implementation of Embedded System Standards
Michael Lucas (Northrop Grumman ESSD)
Poster B.1 Network Operating Systems
Timothy Boggess ( Sanders, A Lockheed martin Company)
David Friedland (Spectron Microsystems)
Poster B.2 Portable Message Passing Software and Tools for Embedded Environments
Robert Cunningham (MIT Lincoln Laboratory)
Rob Steele (MIT Lincoln Laboratory)
Rich Green (MIT Lincoln Laboratory)
Poster B.3 An MPI Implementation for Resource Contained Embedded Systems
Nathan Doss Sanders, A Lockheed Martin Company)
Poster B.4 Portability and Scalability Without Sacrificing Performance
Richard Jaenicke (Sky Computers)
Joseph Germann (Sky Computers)
Poster B.5 Portability in a DSP Environment
James  Kulp (Mercury Computer Systems)
Poster B.6 Heterogeneous MPI on the Myrinet Multicomputer
Lloyd Lewins (Hughes Aircraft Company)
Glenn Ladd (Hughes Aircraft Company)
Poster B.7 A High-Level Interference for Real-Time Message Passing Systems
Daya Ataputtu (Scientific Computing Associates)
Nicholas Carriero (Scientific Computing Associates)
Andrew Sherman (Scientific Computing Associates)
Poster B.8 Portability Cost Metrics for High-Performance Embedded Computing Applications Such as Embedded Controllers for Signal Processors
Kenneth Kott (Lockheed Martin, Government Electronic Systems) 
Poster B.9 Portable of Data Parallel Algorithms on a DSP Multiprocessor
Mark Flanzbaum (MITRE)
Paul Husted (MITRE)
Poster B.10 Portable Data and Signal Processor Code in Navy Sonar Systems Upgrades
Gary Corbitt (Hughes  Aircraft Company
Session 6: Real-Time Benchmarks
Richard Games (MITRE)
Potable Communication Algorithms for Implementing SAR
Jinwoo Suh (University of Southern California)
Viktor Prasanna (University of Southern California)
Analysis, Implementation and Performance of a Distributed  Householder QR Factorization
Masahiro Arakawa (MIT Lincoln Laboratory)
An Approach to Benchmarking Multiprocessor DSP Subsytems
Mark Richard (Georgia Institute of Technology)
Stephan Fuss (Georgia Institute of Technology)
Todd Johnson (Georgia Institute of Technology)
Rajaram Krishnamurthy (Georgia Institute of Technology)
Karsten Schwan (Georgia Institute of Technology)
Vijay Madisetti (Georgia Institute of Technology)
Tim Singleton (U.S. Navy / PMS 42800)
Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications
Marc Cambell (Northrop Grumman)