*Denotes outstanding submission
28 September
AUDITORIUM
| Welcome David Martinez / MIT Lincoln Laboratory
| Opening Remarks Robert Bond / MIT Lincoln Laboratory
| Supercomputing: Trends, Performance Measurement, and Opportunities (Invited) Cray Henry / High Performance Computing Modernization Program Presentation
| Session 1: Emerging Technologies Kenneth Teitelbaum / MIT Lincoln Laboratories
| Cognitive Systems (Invited) Robert Graybill / DARPA IPTO Presentation
| Future Prospects for Moore's Law (Invited) Dr. Robert Doering / Texas Instruments Abstract || Presentation
| Break
| The Evaluation of GPU-Based Programming Environments for Knowledge Discovery John Johnson / Lawrence Livermore National Library Randall Frank / Lawrence Livermore National Library Sheila Vaidya / Lawrence Livermore National Library Abstract || Presentation
| Sustaining the Exponential Growth of Embedded Digital Signal Processing Capability Gary Shaw / MIT Lincoln Laboratory Mark Richards / Georgia Institute of Technology Abstract || Presentation
| Poster / Demo A: High Level Environments and Interconnects Albert Reuther / Lincoln Laboratory
Poster Session A Précis
Poster A.1 | Application-Specific Optical Interconnects for Embeddd Multiprocessors Neal Bambha / U.S. Army Research Lab Shuvra Bhattacharyya / University of Maryland, College Park Abstract || Précis || Poster
Poster A.2 | Software Architecture for Morphing in Polymorphous Computing Architectures Dan Campbell / Georgia Institute of Technology Dennis Cottel / SPAWAR Systems Center Randall Judd / SPAWAR Systems Center Mark Richards / Georgia Institute of Technology Abstract || Précis || Poster
Poster A.3 | Parallel Matlab: RTExpress on 64-bit SGI Altix with SCSL and MPT Cosmo Castellano / Integrated Systems Abstract || Précis || Poster
Poster A.4 | pMatlab Takes the HPCchallenge Ryan Haney / MIT Lincoln Laboratory Andrew Funk / MIT Lincoln Laboratory Jeremy Kepner / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Charles Rader / MIT Lincoln Laboratory Albert Reuther / MIT Lincoln Laboratory Nadya Travinin / MIT Lincoln Laboratory Abstract || Précis || Poster
Poster A.5 | Gedae: Auto Coding to a Virtual Machine William Lundgren / Gedae, Inc. Kerry Barnes / Gedae, Inc. James Steed / Blue Horizon Development Software Abstract || Précis || Poster
Poster A.6 | Requirements for Scalable Application Specific Processing in Commercial HPEC Steve Miller / Silicon Graphics, Inc. Abstract || Précis || Poster
Poster A.7 | Benchmarking Microprocessors for High-End Signal Processing Stephen Paavola / SKY Computers, Inc. Abstract || Précis || Poster
Poster A.8 | Processing Challenges in Shrinking HPEC Systems into Small UAVs Stephen Pearce / Mercury Computer Systems, Inc. Richard Jaenicke / Mercury Computer Systems, Inc. Abstract || Précis || Poster
Poster A.9 | Implementing Modal Software in Data Flow for Heterogeneous Architectures James Steed / Gedae, Inc. Kerry Barnes / Gedae, Inc. William Lundgren / Gedae, Inc. Abstract || Précis || Poster
Poster A.10 | The Devlopment of a Tactical Environmental Processor (TEP) Open Architecture (OA) Application Using Middleware Standard APIs Bonnie Vena / Lockheed Martin MS&S Carl Barberi / Lockheed Martin MS&S Steve Paavola / SKY Computers, Inc.
| Session 2: Novel Systems Michael Harris / BAE Space Systems IEWS | Focus 1: Advanced Software Optimization David Cousins / BBN Technolgoies
| * | Deployment of SAR and GMTI Signal Processing on a Boeing 707 Aircraft using pMatlab and a Bladed Linux Cluster Jeremy Kepner / MIT Lincoln Laboratory Tim Currie / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Bipin Mathew / MIT Lincoln Laboratory Andrew McCabe / MIT Lincoln Laboratory Michael Moore / MIT Lincoln Laboratory Daniel Rabinkin / MIT Lincoln Laboratory Albert Reuther / MIT Lincoln Laboratory Andrew Rhoades / MIT Lincoln Laboratory Louis Tella / MIT Lincoln Laboratory Nadya Travinn / / MIT Lincoln Laboratory Abstract || Presentation | Discrete Fourier Transform IP Generator Grace Nordin / Carnegie Mellon University James Hoe / Carnegie Mellon University Markus Pueschel / Carnegie Mellon University Abstract || Presentation
| Virtual Prototyping and Performance Analysis of RapdIO-Based System Architectures for Space-Based Radar David Bueno / University of Florida Chris Conger / University of Florida Alan George / University of Florida Adam Leko / University of Florida Ian Troxel / University of Florida Abstract || Presentation | Mapping Signal Processing Kernels to Tiled Architectures Henry Hoffman / MIT Lincoln Laboratory James Lebak / MIT Lincoln Laboratory Abstract || Presentation
| Kronecker-FFT Algorithms for Multidimensional SAR PSF Processing Domingo Rodriquez / University of Puerto Rico Abstract | A Transformational Approach to High Performance Embedded Computing Wim Bohm / Colorado State University Jeff Hammes / SRC Computers, Inc. Abstract || Presentation
| A KASSPER Real-Time Signal Processor Testbed Glen Schrader / MIT Lincoln Laboratory Abstract || Presentation | Adaptive Mapping of Linear DSP Algorithms to Fixed-Point Arithmetic Lawrence Chang / Carnegie Mellon University Markus Pueschel / Carnegie Mellon University Yevgen Voronenko / Carnegie Mellon University Abstract || Presentation
| HPCS HPCchallenge Benchmark Suite David Koester / The MITRE Corporation Jack Dongarra / University of Tennessee Piotr Luszczek / Innovative Computing Laboratory Abstract || Presentation | Language-level Transactions for Modular Reliable Systems C. Scott Ananian / MIT CSAIL Martin Rinard / MIT CSAIL Abstract || Presentation
|  | SAE AADL: An Industry Standard for Predictable Embedded Real-Time Systems Engineering (Invited) Peter Feiler / Carnegie Mellon University Presentation
| Banquet Presentation Area-Time-Power Tradeoffs in Computer Design: The Road Ahead Dr. Michael Flynn / Stanford University Presentation
29 September
| Announcements Robert Bond / MIT Lincoln Laboratory
| Keynote Address Why Latency Lags Bandwidth, and What It Means to Computing Dr. David Patterson / University of California, Berkeley Presentation
| Session 3: FPGAs John Grosh / OSD
| Industry Chip Hardware Technology (Invited) H. Peter Hofstee / IBM
| FPGA Acceleration of Information Management Services Richard Linderman / AFRL Chun-Shin Lin / University of Missouri, Columbia Mark Linderman / AFRL Abstract || Presentation
| A Systolic FFT Architecture for Real Time FPGA Systems Preston Jackson / MIT Lincoln Laboratory Cy Chan / MIT Lincoln Laboratory Charles Rader / MIT Lincoln Laboratory Jonathan Scalera / MIT Lincoln Laboratory Michael Vai / MIT Lincoln Laboratory Abstract || Presentation
| Variable Precision Floating Point Division and Square Root Miriam Leeser / Northeastern University Albert Conti / Northeastern University Xiaojun Wang / Northeastern University Abstract || Presentation
| Poster / Demo B: Dynamic Hardware Michael Vai / MIT Lincoln Laboratory
Poster Session B Précis
Poster B.1 | Automated Incremental Design of Flexible Instrusion Detection Systems on FPGAs Zachary Baker / University of Southern California Viktor Prasanna / University of Southern California Ronald Scrofano / University of Southern California Abstract || Précis || Presentation
Poster B.2 | Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components Graham Bardouleau / Mercury Computer Systems, Inc. James Kulp / Mercury Computer Systems, Inc. Abstract || Précis || Presentation
Poster B.3 | An Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs Tom Dillon / Dillon Engineering Abstract || Précis || Presentation
Poster B.4 | MONARCH: Next Generation SoC (Supercomputer on a Chip) John Granacki / University of Southern California Abstract || Précis
Poster B.5 | Sparse Linear Solver for Power System Analysis using FPGA Jeremy Johnson / Drexel University Prawaat Nagvajara / Drexel University Chika Nwankpa / Drexel University Abstract || Précis || Presentation
Poster B.6 | Initial Kernel Timing Using a Simple PIM Performance Model Daniel Katz / NASA Jet Propulsion Laboratory Gary Block / NASA Jet Propulsion Laboratory Jay Brockman / University of Notre Dame David Callahan / Cray, Inc. Paul Springer / NASA Jet Propulsion Laboratory Thomas Sterling / Center for Advanced Computing Research Abstract || Précis || Presentation
Poster B.7 | CASE STUDY: Using Field Programmable Gate Arrays in a Beowulf Cluster Matthew Krzych / NUWC Abstract || Précis || Presentation
Poster B.8 | The World's First Commercially-Available Stream Processor; Architecture, Algorithms and Benchmark Results Simon McIntosh-Smith / ClearSpeed Technology Ron Bell / AWE Aldermaston Abstract || Précis || Presentation
Poster B.9 | High Performance Embedded Computing using Field Programmable Gate Arrays Craig Petrie / Nallatech, Ltd. Charlie Cump / Nallatech, Ltd. Malachy Devlin / Nallatech, Ltd. Keith Regester / Nallatech, Ltd. Abstract || Précis || Presentation
Poster B.10 | Dynamo: A Runtime Codesign Environment Heather Quinn / Northeastern University Laurie King / College of the Holy Cross Miriam Leeser / Northeastern University Abstract || Précis || Presentation
Poster B.11 | Hardware Benchmark Results for An Ultra-High Performance Architecture for Embedded Defense Signal and Image Processing Applications Stewart Reddaway / WorldScape Defense Co. Brad Atwater / Lockheed Martin MS&S Paul Bruno / WorldScape Defense Co. Dairsie Latimer / ClearSpeed Technology, Ltd. Rick Pancoast / Lockheed Martin NE&SS Pete Rogina / WorldScape, Inc. Abstract || Précis || Presentation
Poster B.12 | Developing Energy-Aware Strategies for the Blackfin Processor Steven VanderSanden / Northeastern University Richard Gentile / Analog Devices, Inc. David Kaeli / Northeastern University Giuseppe Olivadoti / Analog Devices, Inc. Abstract || Précis || Presentation
| Session 4: Hardware Architecture Rick Pancoast / Lockheed Martin | Focus 2: Parallel Software Cleve Moler / The MathWorks, Inc.
| Microarchitecture Optimization for Embedded Systems David Schuehler / Washington University Benjamin Brodie / Washington University Roger Chamberlain / Washington University Ron Cytron / Washington University Scott Friedman / Washington University Jason Fritts / Washington University Phillip Jones / Washington University Praveen Krishnamurthy / Washington University John Lockwood / Washington University Shobana Padmanabhan / Washington University Huakai Zhang / Washington University Abstract || Presentation | LLgrid: Enabling On-Demand Grid Computing with gridMatlab and pMatlab Albert Reuther / MIT Lincoln Laboratory Tim Currie / MIT Lincoln Laboratory Jeremy Kepner / MIT Lincoln Laboratory Hahn Kim / MIT Lincoln Laboratory Andrew McCabe / MIT Lincoln Laboratory Michael Moore / MIT Lincoln Laboratory Nadya Travinin / MIT Lincoln Laboratory Abstract || Presentation
| Versatile Tiled-Processor Architecture: The Raw Approach Rodric Rabbah / MIT Anant Agarwal / MIT Ian Bratt / MIT Abstract || Presentation | Parallel Matlab Computation for STAP Clutter Scattering Function Estimation and Moving Target Estimation Roger Chamberlain / Washington University Lisandro Boggio / Washington University Daniel Fuhrmann / Washington University John Maschmeyer / Washington University Abstract || Presentation
| Proposed Parallel Architecture for Matrix Triangularization with Diagonal Loading Charles Rader / MIT Lincoln Laboratory Abstract || Presentation | Star-P: High Productivity Parallel Computing Ron Choy / MIT CSAIL David Cheng / MIT CSAIL Alan Edelman / MIT CSAIL John Gilbert / University of California, Santa Barbara Virai Shah / University of California, Santa Barbara Abstract || Presentation
| Panel: Amending Moore's Law for Embedded Applications Moderator: Dr. James C. Anderson / MIT Lincoln Laboratory - Presentation Distinguished Panelists: - Mr. David Martinez / MIT Lincoln Laboratory - Presentation - Dr. Richard Linderman / AFRL - Presentation - Prof. Robert Schaller / College of Southern Maryland - Presentation - Dr. Mark Richards / Georgia Institute of Technology - Presentation
30 September
| Announcements Robert Bond / MIT Lincoln Laboratory
| From a Federated to an Integrated Architecture for Dependable Embedded Systems (Invited) Dr. Hermann Kopetz / Institut fur Technnische Informatik Presentation
| Session 5: Standards Overview Craig Lund / Mercury Computer Systems, Inc. Presentation
| GPUs: Engines for Future High-Performance Computing (Invited) John Owens / University of California at Davis Presentation
| OMG Data-Distribution Service (DDS): Architectural Overview Gerardo Pardo-Castellote / Real-Time Innovations Abstract || Presentation
| High Productivity MPI - Grid, Multi-Cluster, and Embedded System Extensions Pirabbhu Raman / Verari Systems Software, Inc. Puri Banglore / Verari Systems Software, Inc. Rossen Dimitrov / Verari Systems Software, Inc. Kumaran Rajaram / Verari Systems Software, Inc. Anthony Skjellum / Verari Systems Software, Inc. Abstract || Presentation
| HPEC Related VITA Standards: An Update Randy Banton / Mercury Computers Presentation
| DigitalIF Interface Standardization Paul Mesibov / Pentek Presentation
| Poster / Demo C: Software Stephen Paavola / SKY Computers, Inc.
Poster Session C Précis
Poster C.1 | An Overview of the Common Component Architecture Rob Armstrong / Sandia National Laboratory David Bernholdt / Oak Ridge National Laboratory Teresa Ko / Sandia National Laboratory Abstract || Poster
Poster C.2 | Performance Analysis of Real-Time CORBA on RapidIO Bill Beckwith / Objective Interface Systems, Inc. Kevin Buesing / Objective Interface Systems, Inc.i
Poster C.3 | High-Assurance Security/Safety on HPEC Systems: An Oxymoron? Bill Beckwith / Objective Interface Systems, Inc. Mark Vanfleet / National Security Agency Abstract || Précis
Poster C.4 | Pulse Compression Made Easy with VSIPL++ Brian Chase / Verari Systems Software Dave Leimbach / Verari Systems Software Rick Pancoast / Lockheed Martin NE&SS Anthony Skjellum / Verari Systems Software Wenhao Wu / Verari Systems Software Abstract || Précis || Poster
Poster C.5 | Optimised MPI for HPEC Applications Gerard Cristau / Thales Computers Vincent Chuffart / Thales Computers Abstract || Précis || Poster
Poster C.6 | Implementing the Matrix Exponential Function on Embedded Processors James Lebak / MIT Lincoln Laboratory Andrea Wadell / MIT Lincoln Laboratory Abstract || Précis || Poster
Poster C.7 | R-Stream: Compiler Technology for Next Generation HPEC Richard Lethin / Reservoir Labs, Inc. Peter Mattson / Reservoir Labs, Inc. Abstract || Précis || Poster
Poster C.8 | Utility Accrual Scheduling of Distributable Threads: The Tempus Approach Peng Li / Virginia Polytechnic Institute E. Douglas Jensen / The MITRE Corporation Binoy Ravindran / Virginia Polytechnic Institute Abstract
Poster C.9 | Optimizing the Fast Fourier Transform Over Memory Hierarchies for Embedded Digital Systems: A Fully In-Cache Algorithm James Reynolds / SUNY, Albany Lenore Mullin / SUNY, Albany Abstract || Poster | Figure 1 | Figure 2
Poster C.10 | Time-Frequency Analysis for Single Channel Applications John Saunders / Mercury Computers Abstract || Précis || Poster
Poster C.11 | Model Driven Architectures and UML Performance Modeling Capability - Design and Usage Leonard Weinberg / Lockheed Martin MS&S Harald Pschunder / Lockheed Martin MS&S Michael Stebnisky / Lockheed Martin ATL Abstract || Précis || Poster
| Focus 3: HPEC - Software Initiative Jeremy Kepner / MIT Lincoln Laboratory
| VSIPL++: Parallel Performance Mark Mitchell / CodeSourcery, LLC Jeffrey Oldham / CodeSourcery, LLC Abstract || Presentation
| Evaluation of the VSIPL++ Serial Specification using the DADS Beamformer Dennis Cottell / SPAWAR Systems Center Randall Judd / SPAWAR Systems Center Abstract || Presentation
| Implementation of a Shipboard Ballistic Missile Defense Processing Application using the High Performance Embedded Computing Software Initiative (HPEC-SI) API Joe Cook / Lockheed Martin NE&SS Nathan Doss / Lockheed Martin NE&SS Jane Kent / Lockheed Martin NE&SS Jeremy Kepner / MIT Lincoln Laboratory Rick Pancoast / Lockheed Martin NE&SS Abstract || Presentation
| Adjourn